May 20, 2022

Botu Linum

The Car & Automotive Devotees

AMD’s Future CPUs Could Feature a 3D-Stacked ML Accelerator

5 min read

AMD has patented a processor featuring a machine learning (ML) accelerator that is stacked on top of its I/O die (IOD). The patent indicates that AMD may be planning to build special-purpose or datacenter system-on-chips (SoCs) with integrated FPGA or GPU-based machine learning accelerators.

Just like AMD can now add cache to its CPUs, it might add an FPGA or GPU on top of its processor I/O die. But, more importantly, the technology allows the company to add other types of accelerators to future CPU SoCs. As with any patented work, the patent doesn’t guarantee that we’ll see designs with the tech come to market. However, it gives us a view into what direction the company is moving with its R&D, and there is a chance we could see products based on this tech, or a close derivative, come to market. 

Stacking AI/ML Accelerator on Top of an I/O Die

AMD’s patent titled ‘Direct-connected machine learning accelerator’ rather openly describes how AMD might add an ML-accelerator to its CPUs with an IOD using its stacking technologies. Apparently, AMD’s technology allows it to add a field-programmable processing array (FPGA) or a compute GPU for machine learning workloads on top of an I/O die with a special accelerator port. 

https://www.tomshardware.com/news/amd-future-cpus-could-feature-direct-attached-accelerators